Commands For Sdio Card Devices - Altera cyclone V Technical Reference

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Commands for SDIO Card Devices

8. The internal DMA controller fetches the data from the FIFO buffer and transfers the data to system
memory.
9. When data spans across multiple descriptors, the internal DMA controller fetches the next descriptor
and continues with its operation with the next descriptor. The Last Descriptor bit in the descriptor
indicates whether the data spans multiple descriptors or not.
10.When data reception is complete, status information is updated in the
bit to 1, if enabled. Also, the OWN bit is set to 0 by the DMA controller by updating the DES0 field of
the descriptor.
Commands for SDIO Card Devices
This section describes the commands to temporarily halt the transfers between the controller and SDIO
card device.
Suspend and Resume Sequence
For SDIO cards, a data transfer between an I/O function and the controller can be temporarily halted
using the SUSPEND command. This capability might be required to perform a high-priority data transfer
with another function. When desired, the suspended data transfer can be resumed using the RESUME
command.
The SUSPEND and RESUME operations are implemented by writing to the appropriate bits in the CCCR
(Function 0) of the SDIO card. To read from or write to the CCCR, use the controller's IO_RW_DIRECT
command.
Suspend
To suspend data transfer, perform the following steps:
1. Check if the SDIO card supports the SUSPEND/RESUME protocol by reading the SBS bit in the CCCR
at offset 0x08 of the card.
2. Check if the data transfer for the required function number is in process. The function number that is
currently active is reflected in the function select bits (FSx) of the CCCR, bits 3:0 at offset 0x0D of the
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card.
Note: If the bus status bit (BS), bit 0 at address 0xC, is 1, only the function number given by the FSx
bits is valid.
3. To suspend the transfer, set the bus release bit (BR), bit 2 at address 0xC, to 1.
4. Poll the BR and BS bits of the CCCR at offset 0x0C of the card until they are set to 0. The BS bit is 1
when the currently-selected function is using the data bus. The BR bit remains 1 until the bus release is
complete. When the BR and BS bits are 0, the data transfer from the selected function is suspended.
5. During a read-data transfer, the controller can be waiting for the data from the card. If the data transfer
is a read from a card, the controller must be informed after the successful completion of the SUSPEND
command. The controller then resets the data state machine and comes out of the wait state. To
accomplish this, set the abort read data bit (
6. Wait for data completion, by polling until the
the number of pending bytes to transfer, read the transferred CIU card byte count (
the controller. Subtract this value from the total transfer size. You use this number to resume the
transfer properly.
Resume
To resume the data transfer, perform the following steps:
Altera Corporation
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) in the
abort_read_data
bit is set to 1 in the
dto
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register by setting the
idsts
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register to 1.
ctrl
register. To determine
rintsts
) register of
tcbcnt
SD/MMC Controller
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2016.10.28
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