Altera cyclone V Technical Reference page 808

11-70
protruledata
31 30
15 14
highid
RW 0x0
protruleid Fields
Bit
23:12
highid
11:0
lowid
protruledata
This register configures the protection memory characteristics of each protection rule.
Module Instance
sdr
Offset:
0x5098
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
Reserved ruler
esult
Altera Corporation
29 28 27 26
Reserved
13 12 11 10
Name
AxID for the protection rule. Incoming AxID needs
to be less than or equal to this value. For all AxIDs
from a port, AxID high should be programmed to all
ones.
AxID for the protection rule. Incoming AxID needs
to be greater than or equal to this value. For all AxIDs
from a port, AxID high should be programmed to all
ones.
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
RW
0x0
Bit Fields
25 24 23 22
9 8 7 6
Description
Base Address
0xFFC20000
Bit Fields
25 24 23 22
Reserved
9 8 7 6
portmask
RW 0x0
21 20 19 18
highid
RW 0x0
5 4 3
lowid
RW 0x0
Register Address
0xFFC25098
21 20 19 18
5 4 3
valid
rule
RW
0x0
SDRAM Controller Subsystem
cv_5v4
2016.10.28
17 16
2 1 0
Access Reset
RW 0x0
RW 0x0
17 16
2 1 0
security
RW 0x0
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