Altera cyclone V Technical Reference page 375

cv_5v4
2016.10.28
GPLMUX7 Fields
Bit
0
sel
GPLMUX8
Selection between GPIO and LoanIO output and output enable for GPIO8 and LoanIO8. These signals
drive the Pin Mux. The Pin Mux must be configured to use GPIO/LoanIO in addition to these settings
Only reset by a cold reset (ignores warm reset). NOTE: These registers should not be modified after IO
configuration.There is no support for dynamically changing the Pin Mux selections.
Module Instance
sysmgr
Offset:
0x5F4
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
GPLMUX8 Fields
Bit
0
sel
System Manager
Send Feedback
Name
Select source for GPIO/LoanIO 7. 0 : LoanIO 7
controls GPIO/LOANIO[7] output and output enable
signals. 1 : GPIO 7 controls GPIO/LOANI[7] output
and output enable signals.
0xFFD08000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Name
Select source for GPIO/LoanIO 8. 0 : LoanIO 8
controls GPIO/LOANIO[8] output and output enable
signals. 1 : GPIO 8 controls GPIO/LOANI[8] output
and output enable signals.
Description
Base Address
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Reserved
Description
GPLMUX8
Access
Register Address
0xFFD085F4
21 20 19 18
5 4 3 2
Access
5-181
Reset
RW 0x0
17 16
1 0
sel
RW 0x0
Reset
RW 0x0
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