Altera cyclone V Technical Reference page 867

13-46
int_mon_cyccnt
erase_wait_cnt Fields
Bit
15:0
value
int_mon_cyccnt
Interrupt monitor cycle count value
Module Instance
nandregs
Offset:
0x50
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
int_mon_cyccnt Fields
Bit
15:0
value
Altera Corporation
Name
Number of clock cycles after issue of erase operation
before NAND Flash Controller polls for status. This
values is of relevance for status polling mode of
operation and has been provided to minimize
redundant polling after issuing a command. After a
erase command, the first polling will happen after this
many number of cycles have elapsed and then on
polling will happen every int_mon_cyccnt cycles. The
default values is equal to the default value of int_
mon_cyccnt. The controller internally multiplies the
value programmed into this register by 16 to provide
a wider range for polling.
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Name
In polling mode, sets the number of cycles Denali
Flash Controller must wait before checking the status
register. This register is only used when R/B pins are
not available to NAND Flash Controller.
Description
Base Address
0xFFB80000
Bit Fields
25 24 23 22
Reserved
9 8 7 6
value
RW 0x1F4
Description
Access
Register Address
0xFFB80050
21 20 19 18
5 4 3 2
Access
NAND Flash Controller
cv_5v4
2016.10.28
Reset
RW 0x1F4
17 16
1 0
Reset
RW 0x1F4
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