Altera cyclone V Technical Reference page 14

TOC-14
CAN Controller Programming Model..................................................................................................25-12
CAN Controller Address Map and Register Definitions....................................................................25-14
Document Revision History.................................................................................................................25-233
Introduction to the HPS Component............................................................... 26-1
MPU Subsystem......................................................................................................................................... 26-2
ARM CoreSight Debug Components......................................................................................................26-2
Interconnect................................................................................................................................................26-2
HPS-to-FPGA Interfaces...........................................................................................................................26-2
Memory Controllers.................................................................................................................................. 26-3
Support Peripherals....................................................................................................................................26-3
Interface Peripherals.................................................................................................................................. 26-3
On-Chip Memories....................................................................................................................................26-4
Document Revision History.....................................................................................................................26-4
Instantiating the HPS Component................................................................... 27-1
FPGA Interfaces......................................................................................................................................... 27-1
Configuring HPS Clocks and Resets....................................................................................................... 27-8
Configuring Peripheral Pin Multiplexing............................................................................................. 27-11
Configuring the External Memory Interface........................................................................................27-14
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DMA Mode..................................................................................................................................... 25-8
Automatic Retransmission............................................................................................................25-8
Test Mode........................................................................................................................................ 25-8
L4 Slave Interface......................................................................................................................... 25-10
Clocks............................................................................................................................................ 25-10
Software Reset...............................................................................................................................25-10
Hardware Reset............................................................................................................................ 25-11
Interrupts...................................................................................................................................... 25-11
Software Initialization................................................................................................................. 25-12
CAN Message Transfer................................................................................................................25-13
Message Object Reconfiguration for Frame Reception.......................................................... 25-13
Message Object Reconfiguration for Frame Transmission.................................................... 25-14
CAN Controller Module Address Map.....................................................................................25-15
General Interfaces.......................................................................................................................... 27-2
FPGA-to-HPS SDRAM Interface.................................................................................................27-3
DMA Peripheral Request.............................................................................................................. 27-5
Interrupts.........................................................................................................................................27-5
AXI Bridges.....................................................................................................................................27-7
User Clocks..................................................................................................................................... 27-8
Reset Interfaces...............................................................................................................................27-9
PLL Reference Clocks..................................................................................................................27-10
Peripheral FPGA Clocks............................................................................................................. 27-11
Configuring Peripherals.............................................................................................................. 27-12
Connecting Unassigned Pins to GPIO......................................................................................27-12
Using Unassigned IO as LoanIO................................................................................................27-13
Resolving Pin Multiplexing Conflicts........................................................................................27-13
Peripheral Signals Routed to FPGA ..........................................................................................27-13