Altera cyclone V Technical Reference page 159

Hard processor system

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This field determines the Configuration Passive

Parallel data bus width when HPS configures the

FPGA. Only 32-bit Passive Parallel or 16-bit Passive

Parallel are supported. When HPS does Normal

Configuration, configuration should use 32-bit

Passive Parallel Mode. The external pins MSEL must

be set appropriately for the configuration selected. For

Partial Reconfiguration, 16-bit Passive Parallel must

There are strict SW initialization steps for configura‐

tion, partial configuration and error cases. When SW

is sending configuration files, this bit must be set

before the file is transferred on the AXI bus. This bit

enables the DCLK during the AXI configuration data

transfers. Note, the AXI and configuration datapaths

remain active irregardless of the state of this bit.

Simply, if the AXI slave is enabled, the DCLK to the

CB will be active. If disabled, the DCLK to the CB will

not be active. So AXI transfers destined to the FPGA

Manager when AXIEN is 0, will complete normally

from the HPS perspective. This field only affects the

FPGA if CTRL.EN is 1.

16-bit Passive Parallel

32-bit Passive Parallel

Incoming AXI data transfers will be ignored.

DCLK will not toggle during data transfer.

AXI data transfer to CB is active. DCLK will

toggle during data transfer.

FPGA Manager

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