Altera cyclone V Technical Reference page 783

cv_5v4
2016.10.28
protportdefault
This register controls the default protection assignment for a port. Ports which have explicit rules which
define regions which are illegal to access should set the bits to pass by default. Ports which have explicit
rules which define legal areas should set the bit to force all transactions to fail. Leaving this register to all
zeros should be used for systems which do not desire any protection from the memory controller.
protruleaddr
This register is used to control the memory protection for port 0 transactions. Address ranges can either be
used to allow access to memory regions or disallow access to memory regions. If TrustZone is being used,
access can be enabled for protected transactions or disabled for unprotected transactions. The default state
of this register is to allow all access. Address values used for protection are only physical addresses.
protruleid
This register configures the AxID for a given protection rule.
protruledata
This register configures the protection memory characteristics of each protection rule.
protrulerdwr
This register is used to perform read and write operations to the internal protection table.
mppriority
This register is used to configure the DRAM burst operation scheduling.
remappriority
This register applies another level of port priority after a transaction is placed in the single port queue.
Port Sum of Weight Register Register Descriptions
This register is used to configure the DRAM burst operation scheduling.
ctrlcfg
The Controller Configuration Register determines the behavior of the controller.
Module Instance
sdr
Offset:
0x5000
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
SDRAM Controller Subsystem
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0xFFC20000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
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Base Address
0xFFC25000
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ctrlcfg
Register Address
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