Altera cyclone V Technical Reference page 103

2-66
ctrl
Bit
2
pwrdn
1
en
0
bgpwrdn
ctrl
Contains VCO control signals and other PLL control signals need to be controllable through register.
Fields are only reset by a cold reset.
Module Instance
clkmgr
Offset:
0xC4
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
Reserved saten faste
RW
0x1
ctrl Fields
Bit
14
saten
13
fasten
12:1
bwadj
Altera Corporation
Name
If '1', power down analog circuitry. If '0', analog
circuitry not powered down.
If '1', VCO is enabled. If '0', VCO is in reset.
If '1', powers down bandgap. If '0', bandgap is not
power down.
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
n
RW
0x0
Name
Enables saturation behavior.
Enables fast locking circuit.
Provides Loop Bandwidth Adjust value.
Description
Base Address
0xFFD04000
Bit Fields
25 24 23 22
Reserved
9 8 7 6
bwadj
RW 0x1
Description
Access
Register Address
0xFFD040C4
21 20 19 18
5 4 3 2
Access
cv_5v4
2016.10.28
Reset
RW 0x1
RW 0x0
RW 0x1
17 16
1 0
bwadjen
RW 0x0
Reset
RW 0x1
RW 0x0
RW 0x1
Clock Manager
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