Altera cyclone V Technical Reference page 569

cv_5v4
2016.10.28
EMAC1 Register Descriptions
Registers associated with the EMAC1 slave interface. This slave is used by the DMA controller built into
the EMAC1 to access slaves attached to the L3/L4 Interconnect.
Offset:
0x7000
read_qos on page 7-121
QoS (Quality of Service) value for the read channel.
write_qos
QoS (Quality of Service) value for the write channel.
fn_mod on page 7-122
Sets the block issuing capability to multiple or single outstanding transactions.
read_qos
QoS (Quality of Service) value for the read channel.
Module Instance
l3regs
Offset:
0x49100
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
read_qos Fields
Bit
3:0
pri
write_qos
QoS (Quality of Service) value for the write channel.
System Interconnect
Send Feedback
on page 7-121
0xFF800000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Reserved
Name
QoS (Quality of Service) value for the read channel. A
higher value has a higher priority.
Base Address
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Description
EMAC1 Register Descriptions
Register Address
0xFF849100
21 20 19 18
5 4 3 2
RW 0x0
Access
7-121
17 16
1 0
pri
Reset
RW 0x0
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