Altera cyclone V Technical Reference page 15

Selecting PLL Output Frequency and Phase............................................................................ 27-15
Using the Address Span Extender Component....................................................................................27-15
Generating and Compiling the HPS Component............................................................................... 27-16
Document Revision History...................................................................................................................27-17
HPS Component Interfaces...............................................................................28-1
Memory-Mapped Interfaces.....................................................................................................................28-1
FPGA-to-HPS Bridge.................................................................................................................... 28-1
HPS-to-FPGA and Lightweight HPS-to-FPGA Bridges...........................................................28-2
FPGA-to-HPS SDRAM Interface.................................................................................................28-3
Clocks.......................................................................................................................................................... 28-4
Alternative Clock Inputs to HPS PLLs........................................................................................ 28-4
User Clocks..................................................................................................................................... 28-4
AXI Bridge FPGA Interface Clocks............................................................................................. 28-5
SDRAM Clocks.............................................................................................................................. 28-5
Peripheral FPGA Clocks............................................................................................................... 28-5
Resets........................................................................................................................................................... 28-6
HPS-to-FPGA Reset Interfaces.................................................................................................... 28-6
HPS External Reset Request......................................................................................................... 28-6
Peripheral Reset Interfaces............................................................................................................28-7
Debug and Trace Interfaces...................................................................................................................... 28-7
Trace Port Interface Unit...............................................................................................................28-7
FPGA System Trace Macrocell Events Interface........................................................................28-7
FPGA Cross Trigger Interface...................................................................................................... 28-7
Debug APB Interface..................................................................................................................... 28-7
Peripheral Signal Interfaces...................................................................................................................... 28-7
DMA Controller Interface............................................................................................................ 28-7
Other Interfaces..........................................................................................................................................28-8
MPU Standby and Event Interfaces.............................................................................................28-8
General Purpose Signals............................................................................................................... 28-9
FPGA-to-HPS Interrupts.............................................................................................................. 28-9
Boot from FPGA Interface............................................................................................................28-9
Input-only General Purpose Interface........................................................................................ 28-9
Document Revision History.....................................................................................................................28-9
Simulating the HPS Component.......................................................................29-1
Simulation Flows........................................................................................................................................29-2
Setting Up the HPS Component for Simulation........................................................................29-3
Generating the HPS Simulation Model in Qsys........................................................................ 29-5
Running the Simulations...............................................................................................................29-5
Clock and Reset Interfaces........................................................................................................................29-9
Clock Interface............................................................................................................................... 29-9
Reset Interface.............................................................................................................................. 29-10
FPGA-to-HPS AXI Slave Interface........................................................................................................ 29-11
HPS-to-FPGA AXI Master Interface.....................................................................................................29-11
Lightweight HPS-to-FPGA AXI Master Interface...............................................................................29-12
FPGA-to-HPS SDRAM Interface.......................................................................................................... 29-13
TOC-15
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