Altera cyclone V Technical Reference page 148

Hard processor system

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Table 4-1: Configuration Schemes for FPGA Configuration by the HPS

sion Feature

HPS software sets the clock-to-data ratio field (

the control register (

the start of configuration.

The FPGA manager connects to the configuration logic in the FPGA portion of the device using a mode

similar to how external logic (for example, MAX II or an intelligent host) configures the FPGA in fast

For information about POR delay, refer to the Configuration, Design Security, and Remote System Upgrades

in Cyclone V Devices.

Other MSEL values are allowed when the FPGA is configured from a non-HPS source. For information, refer

to the Configuration, Design Security, and Remote System Upgrades in Cyclone V Devices.

You can select to enable or disable this feature.

When the FPGA is configured through the HPS, then FPPx32 is supported. Otherwise, if the FPGA is

configured from a non-HPS (external) source, then FPPx32 is not supported. For more information refer to

the Configuration, Design Security, and Remote System Upgrades in Cyclone V Devices.

FPGA Manager

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) to match the

) and configuration data width bit (

FPGA Configuration

Reconfiguration

bit must be set before

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