Altera cyclone V Technical Reference page 589

cv_5v4
2016.10.28
Signal
ARUSER
Table 8-7: FPGA-to-HPS Bridge Slave Read Data Channel Signals
Signal
RID
RDATA
RRESP
RLAST
RVALID
RREADY
FPGA2HPS AXI Bridge Module Address Map
Registers in the FPGA2HPS AXI Bridge Module.
Base Address:
ID Register Group
Register
periph_id_4 on page
8-9
periph_id_0 on page
8-9
periph_id_1 on page
8-10
periph_id_2 on page
8-11
periph_id_3 on page
8-11
comp_id_0 on page 8-
12
comp_id_1 on page 8-
13
comp_id_2 on page 8-
13
HPS-FPGA Bridges
Send Feedback
Width Direction
5 bits Input
Width Direction
8 bits Output
32, 64, or 128 bits Output
2 bits Output
1 bit Output
1 bit Output
1 bit Input
0xFF600000
Offset Width Acces
0x1FD0
0x1FE0
0x1FE4
0x1FE8
0x1FEC
0x1FF0
0x1FF4
0x1FF8
FPGA2HPS AXI Bridge Module Address Map
Read user sideband signals
Read ID
Read data
Read response
Read last data identifier
Read data channel valid
Read data channel ready
Reset Value
s
32 RO 0x4
32 RO 0x1
32 RO 0xB3
32 RO 0x6B
32 RO 0x0
32 RO 0xD
32 RO 0xF0
32 RO 0x5
Description
Description
Description
Peripheral ID4 Register
Peripheral ID0 Register
Peripheral ID1 Register
Peripheral ID2 Register
Peripheral ID3 Register
Component ID0 Register
Component ID1 Register
Component ID2 Register
Altera Corporation
8-7