Altera cyclone V Technical Reference page 699

cv_5v4
2016.10.28
AXI ID width on slave ports
Address filtering
Speculative read
Presence of ARUSERMx and AWUSERMx sideband
signals
Related Information
ARM Infocenter
For further information about cache controller configurable options, refer to the CoreLink Level 2 Cache
Controller L2C-310 Technical Reference Manual, available on the ARM Infocenter website.
L2 Cache Event Monitoring
The L2 cache supports the built-in cache event monitoring signals shown in the table below. The L2 cache
can count two of the events at any one time.
Table 9-11: L2 Cache Events
CO
DRHIT
DRREQ
DWHIT
DWREQ
DWTREQ
EPFALLOC
EPFHIT
EPFRCVDS0
Cortex-A9 Microprocessor Unit Subsystem
Send Feedback
Feature
Event
L2 Cache Event Monitoring
Meaning
6 AXI ID bits on slave ports
Address filtering logic enabled
Logic for supporting speculative read enabled
Sideband signals enabled
Description
Eviction (cast out) of a line from the L2 cache.
Data read hit in the L2 cache.
Data read lookup to the L2 cache. Subsequently
results in a hit or miss.
Data write hit in the L2 cache.
Data write lookup to the L2 cache. Subsequently
results in a hit or miss.
Data write lookup to the L2 cache with
write-through attribute. Subsequently results in a hit
or miss.
Prefetch hint allocated into the L2 cache.
Prefetch hint hits in the L2 cache.
Prefetch hint received by slave port S0.
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