Mmc Support Matrix - Altera cyclone V Technical Reference

cv_5v4
2016.10.28

MMC Support Matrix

Table 14-2: MMC Support Matrix
Card Device Type
MMC
RSMMC
MMCPlus
MMCMobile
eMMC
SD/MMC Controller Block Diagram and System Integration
The SD/MMC controller includes a bus interface unit (BIU) and a card interface unit (CIU). The BIU
provides a slave interface for a host to access the control and status registers (CSRs). Additionally, this unit
also provides independent FIFO buffer access through a DMA interface. The DMA controller is
responsible for exchanging data between the system memory and FIFO buffer. The DMA registers are
accessible by the host to control the DMA operation. The CIU supports the SD, MMC, and CE-ATA
protocols on the controller, and provides clock management through the clock control block. The interrupt
control block for generating an interrupt connects to the generic interrupt controller in the ARM Cortex-
A9 microprocessor unit (MPU) subsystem.
Supports a maximum clock rate of 50 MHz instead of 52 MHz (specified in MMC specification)​.
(45)
(46) Optional 8-bit bus mode not supported in all packages.
SD/MMC Controller
Send Feedback
Max Clock Max Data
Speed (MHz) Rate (MBps)
20 2.5
20 10
50 (45) 25
50 6.5
50 25
Voltages Bus Modes
Supported Supported
3.3 V 1.8 V 1 bit
√ √
√ √
√ √
√ √ √
√ √ √
MMC Support Matrix
Bus Speed Modes
Supported
4 bit 8 bit Default
Speed
√
√ √
√ √ (46) √
√
√ √
14-3
High Speed
√
√
√
√
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