Management Interface - Altera cyclone V Technical Reference

cv_5v4
2016.10.28

Management Interface

• 32-bit host interface to CSR set
• Comprehensive status reporting for normal operation and transfers with errors
• Configurable interrupt options for different operational conditions
• Per-frame transmit/receive complete interrupt control
• Separate status returned for transmission and reception packets
Acceleration
• Transmit and receive checksum offload for transmission control protocol (TCP), user datagram
protocol (UDP), or Internet control message protocol (ICMP) over Internet protocol (IP)
PHY Interface
Different external PHY interfaces are provided depending on whether the Ethernet Controller signals are
routed through the HPS I/O pins or the FPGA I/O pins.
The PHY interfaces supported using the HPS I/O pins are:
• Reduced Gigabit Media Independent Interface (RGMII)
The PHY interfaces supported using the FPGA I/O pins are:
• Media Independent Interface (MII)
• Gigabit Media Independent Interface (GMII)
• Reduced Media Independent Interface (RMII) with additional required adaptor logic
Note: Additional adaptor logic for RMII not provided.
• Reduced Gigabit Media Independent Interface (RGMII) with additional required adaptor logic
• Serial Gigabit Media Independent Interface (SGMII) supported through transceiver I/O
The Ethernet Controller has two choices for the management control interface used for configuration and
status monitoring of the PHY:
• Management Data Input/Output (MDIO)
2
• I C PHY management through a separate I
Ethernet Media Access Controller
Send Feedback
2
C module within the HPS
Management Interface
Altera Corporation
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