Dma Controller Block Diagram And System Integration - Altera cyclone V Technical Reference

cv_5v4
2016.10.28
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Using Events and Interrupts

DMA Controller Block Diagram and System Integration

The following figure shows a block diagram of the DMAC and how it integrates into the rest of the HPS
system.
Figure 16-1: DMA Controller Connectivity
DMA Controller
The
l4_main_clk
controller accesses the level 3 (L3) main switch with its 64-bit AXI master interface.
The DMA controller provides the following slave interfaces:
• Non-secure slave interface
• Secure slave interface
You can use these slave interfaces to access the registers that control the functionality of the DMA
controller. Since the DMA controller supports some peripherals that do not comply with the ARM DMA
peripheral interface protocol, some adapters are developed to allow these peripherals to work with the
DMAC.
Functional Description of the DMA Controller
This section describes the major interfaces and components of the DMAC and its operation.
The DMAC contains an instruction processing block that processes program code to control a DMA
transfer. The program code is stored in a region of system memory that the DMAC accesses using its AXI
master interface. The DMAC stores instructions temporarily in an internal cache.
DMA Controller
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on page 16-21
MFIFO
512 x 64
Write Instruction Queue
Read Instruction Queue
Instruction Execution Engine
Instruction Cache
CSRs
Secure
Slave Interface
Level 4 Main Bus
clock drives the DMA controller, controller logic, and all the interfaces. The DMA
DMA Controller Block Diagram and System Integration
Interrupt
Control
Peripheral Request
Interface [30:0]
Reset
Initialization
Interface
Non-Secure
Slave Interface
MPU Subsystem
Generic Interrupt
Controller
Synopsys Adapter
2
UART, SPI, I C, FPGA
and Clock
Peripheral Interfaces
Crossing
Bosch Adapter
and Clock
CAN Peripheral Interface
Crossing
Clock STM and Quad SPI
Peripheral Interfaces
Crossing
System
Manager
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16-3