Altera cyclone V Technical Reference page 799

cv_5v4
2016.10.28
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
lowpwreq Fields
Bit
5:4
selfrfshmask
3
selfrshreq
2:1
deeppwrdnmask
0
deeppwrdnreq
lowpwrack
This register gives the status of the power down commands requested by the Low Power Control register.
Module Instance
sdr
SDRAM Controller Subsystem
Send Feedback
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Reserved
Name
Write a one to each bit of this field to have a self
refresh request apply to both chips.
Write a one to this bit to request the RAM be put into
a self refresh state. This bit is treated as a static value
so the RAM will remain in self-refresh as long as this
register bit is set to a one. This power down mode can
be selected for all DRAMs supported by the
controller.
Write ones to this register to select which DRAM chip
selects will be powered down. Typical usage is to set
both of these bits when deeppwrdnreq is set but the
controller does support putting a single chip into deep
power down and keeping the other chip running.
Write a one to this bit to request a deep power down.
This bit should only be written with LPDDR2
DRAMs, DDR3 DRAMs do not support deep power
down.
0xFFC20000
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Description
Base Address
lowpwrack
21 20 19 18
5 4 3 2
selfrfshmas selfr deeppwrdnma
k shreq
RW 0x0 RW RW 0x0
0x0
Access
Register Address
0xFFC25058
11-61
17 16
1 0
deeppwrd
sk nreq
RW 0x0
Reset
RW 0x0
RW 0x0
RW 0x0
RW 0x0
Altera Corporation