Altera cyclone V Technical Reference page 138

cv_5v4
2016.10.28
Bit Name
17
uart1
16
uart0
15
i2c3
14
i2c2
13
i2c1
12
i2c0
11
sptimer1
10
sptimer0
9
osc1timer1
8
osc1timer0
7
l4wd1
6
l4wd0
5
qspi
4
nand
3
usb1
2
usb0
1
emac1
0
emac0
per2modrst
The PER2MODRST register is used by software to trigger module resets (individual module reset signals).
Software explicitly asserts and de-asserts module reset signals by writing bits in the appropriate *MODRST
register. It is up to software to ensure module reset signals are asserted for the appropriate length of time
and are de-asserted in the correct order. It is also up to software to not assert a module reset signal that
would prevent software from de-asserting the module reset signal. For example, software should not assert
the module reset to the CPU executing the software. Software writes a bit to 1 to assert the module reset
signal and to 0 to de-assert the module reset signal. All fields are reset by a cold or warm reset. The reset
value of all fields is 1. This holds the corresponding module in reset until software is ready to release the
module from reset by writing 0 to its field.
Reset Manager
Send Feedback
Description
Resets UART1
Resets UART0
Resets I2C3 controller
Resets I2C2 controller
Resets I2C1 controller
Resets I2C0 controller
Resets SP timer 1 connected to L4
Resets SP timer 0 connected to L4
Resets OSC1 timer 1 connected to L4
Resets OSC1 timer 0 connected to L4
Resets watchdog 1 connected to L4
Resets watchdog 0 connected to L4
Resets QSPI flash controller
Resets NAND flash controller
Resets USB1
Resets USB0
Resets EMAC1
Resets EMAC0
3-27
per2modrst
Access Reset
RW 0x1
RW 0x1
RW 0x1
RW 0x1
RW 0x1
RW 0x1
RW 0x1
RW 0x1
RW 0x1
RW 0x1
RW 0x1
RW 0x1
RW 0x1
RW 0x1
RW 0x1
RW 0x1
RW 0x1
RW 0x1
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