Implementation Details - Altera cyclone V Technical Reference

9-32

Implementation Details

The ACP ID mapper resides between the interconnect and the ACP slave of the MPU subsystem. It has the
following characteristics:
• Support for up to six concurrent ID mappings
• 1 GB coherent window into 4 GB ARM Cortex-A9 MPCore address space
• Remaps the 5-bit user sideband signals used by the Snoop Control Unit (SCU) and L2 cache
Related Information
ARM Infocenter
For more information about AXI user sideband signals, refer to the CoreLink Level 2 Cache Controller
L2C-310 Technical Reference Manual, available from the ARM Infocenter website.
Implementation Details
The ACP is accessed by masters that require access to coherent memory. The ACP slave port can be
accessed by the master peripherals of the L3 interconnect, as well as by masters implemented in the FPGA
fabric (via the FPGA-to-HPS bridge).
The ACP ID mapper supports the following ID mapping modes:
• Dynamic mapping
• Fixed mapping
Software can select the ID mapping on a per-ID basis. For input IDs that are configured for fixed mapping,
there is a one-to-one mapping from input IDs to output IDs. When an input ID is configured for dynamic
mapping, it is automatically mapped to an available output ID. The dynamic mode is more flexible because
the hardware handles the mapping. The hardware mapping allows you to use one output ID for more than
one input ID. Output IDs are assigned to input IDs on a first-come, first-served basis.
Note: If the number of differently configured masters exceeds the number available in fixed mode, you
must use dynamic mode and ensure that the same
masters.
Out of the total of eight output IDs, only six are available to masters of the system interconnect. The first
two output IDs (0 and 1) are dedicated to the Cortex-A9 processor cores in the MPU subsystem, leaving
the last six output IDs (2-7) available to the ACP ID mapper. Output IDs 2-6 support fixed and dynamic
modes of operation while output ID 7 supports dynamic only.
The operating modes are programmable through accesses to the control and status registers in the ACP ID
mapper. At reset time, the ACP ID mapper defaults to dynamic ID mapping for all output IDs except ID 2,
which resets to a fixed mapping for the Debug Access Port (DAP) input ID.
Related Information
Cortex-A9 MPU Subsystem with System Interconnect
ID Intended Usage
Table 9-7
Altera Corporation
summarizes the expected usage of the 3-bit output IDs, and their settings at reset.
settings are used among all dynamic
AxUSER
on page 9-2
Cortex-A9 Microprocessor Unit Subsystem
cv_5v4
2016.10.28
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