Altera cyclone V Technical Reference page 873

13-52
chip_enable_dont_care
prefetch_mode Fields
Bit
15:4
prefetch_burst_length
0
prefetch_en
chip_enable_dont_care
Device can work in the chip enable dont care mode
Module Instance
nandregs
Offset:
0xD0
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
chip_enable_dont_care Fields
Bit
0
flag
Altera Corporation
Name
If prefetch_en is set and prefetch_burst_length is set
to ZERO, the controller will start prefetching data
only after the receiving the first Map01 read
command for the page. If prefetch_en is set and
prefetch_burst_length is set to a non-ZERO, valid
value, the controller will start prefetching data
corresponding to this value even before the first
Map01 for the current page has been received. The
value written here should be in bytes.
Enable prefetch of Data
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Name
Controller can interleave commands between banks
when this feature is enabled. [list][*]1 - Device in
dont care mode [*]0 - Device cares for chip enable[/
list]
Description
Base Address
0xFFB80000
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Reserved
Description
Access
Register Address
0xFFB800D0
21 20 19 18
5 4 3 2
Access
NAND Flash Controller
cv_5v4
2016.10.28
Reset
RW 0x0
RW 0x1
17 16
1 0
flag
RW 0x0
Reset
RW 0x0
Send Feedback