Altera cyclone V Technical Reference page 91

2-54
pernandsdmmcclk
31 30
15 14
perqspiclk Fields
Bit
8:0
cnt
pernandsdmmcclk
Contains settings that control clock periph_nand_sdmmc_clk generated from the C3 output of the
Peripheral PLL. Only reset by a cold reset.
Module Instance
clkmgr
Offset:
0x94
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
pernandsdmmcclk Fields
Bit
8:0
cnt
Altera Corporation
29 28 27 26
13 12 11 10
Reserved
Name
Divides the VCO frequency by the value+1 in this
field.
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Reserved
Name
Divides the VCO frequency by the value+1 in this
field.
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Description
Base Address
0xFFD04000
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Description
21 20 19 18
5 4 3 2
cnt
RW 0x1
Access
Register Address
0xFFD04094
21 20 19 18
5 4 3 2
cnt
RW 0x1
Access
cv_5v4
2016.10.28
17 16
1 0
Reset
RW 0x1
17 16
1 0
Reset
RW 0x1
Clock Manager
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