Altera cyclone V Technical Reference page 406

5-212
GPLMUX47
31 30
15 14
GPLMUX46 Fields
Bit
0
sel
GPLMUX47
Selection between GPIO and LoanIO output and output enable for GPIO47 and LoanIO47. These signals
drive the Pin Mux. The Pin Mux must be configured to use GPIO/LoanIO in addition to these settings
Only reset by a cold reset (ignores warm reset). NOTE: These registers should not be modified after IO
configuration.There is no support for dynamically changing the Pin Mux selections.
Module Instance
sysmgr
Offset:
0x690
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
Altera Corporation
29 28 27 26
13 12 11 10
Name
Select source for GPIO/LoanIO 46. 0 : LoanIO 46
controls GPIO/LOANIO[46] output and output
enable signals. 1 : GPIO 46 controls GPIO/
LOANI[46] output and output enable signals.
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Reserved
Description
Base Address
0xFFD08000
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Reserved
21 20 19 18
5 4 3 2
Access
Register Address
0xFFD08690
21 20 19 18
5 4 3 2
cv_5v4
2016.10.28
17 16
1 0
sel
RW 0x0
Reset
RW 0x0
17 16
1 0
sel
RW 0x0
System Manager
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