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Altera Cyclone V Boot Manual

Altera Cyclone V Boot Manual

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HPS SoC Boot Guide - Cyclone V SoC Development Kit
2016.01.27
AN-709
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Introduction
This document describes:
• An overview of the boot options available on the Cyclone
• Recommendations to help reduce the boot duration, including measurements of the boot process on
the Cyclone V Development Kit
• Recommendations to help with debugging the boot process
• Bare-metal boot examples that can be run on the Cyclone V SoC Development Kit
Note: Although the document targets Cyclone V, it also applies to Arria
identical between the two families.
Prerequisite
In order to run the examples presented in this Boot Guide the following are required:
• Altera
Cyclone V Development Kit, Rev D
®
• Host PC running Windows 7 or newer
• Altera SoC Embedded Design Suite (SoC EDS), v14.1 installed
• Altera Complete Design Suite (ACDS) v14.1
Note: This document assumes a basic knowledge of Altera SoC EDS, ACDS, Preloader Support Package
Generator (part of SoC EDS) and ARM DS-5 AE.
Related Information
Cyclone V Development Kit and SoC Embedded Design Suite
For more information about the Cyclone V SoC Development board.
SoC EDS Download
For more information about and where to obtain the latest SoC EDS downloads.
ACDS Download
For more information about and where to obtain the latest ACDS downloads.
Altera SoC Embedded Design Suite User Guide
Linux can also be used, with similar commands.
(1)
(2)
Required only for the boot from FPGA example.
Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus and Stratix words and logos are trademarks of
Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current
specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice.
Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly
agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information
and before placing orders for products or services.
*Other names and brands may be claimed as the property of others.
www.altera.com
101 Innovation Drive, San Jose, CA 95134
Send Feedback
(1)
(2)
V
®
V, since the HPS portion is
®
ISO
9001:2008
Registered

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Summary of Contents for Altera Cyclone V

  • Page 1 Required only for the boot from FPGA example. Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice.
  • Page 2 AN-709 Boot Overview 2016.01.27 Boot Overview This chapter presents an overview of the different boot options and capabilities available for the Cyclone V. Boot Flow The following figure depicts the typical boot flow: Figure 1: Typical Boot Flow Additional boot flows are possible, as shown in the following diagram:...
  • Page 3 Currently, two different Preloader options are available: • SPL – part of U-Boot. Provided with SoC EDS under GPL (Open Source) License • MPL – provided with SoC EDS as an example using the HWLibs (Altera bare-metal libraries). Uses BSD license.
  • Page 4 • Raw mode - Preloader images are located at address0 on the card. • Partition mode - Preloader images are located at offset 0 on a custom partition with ID=A2 on the card. HPS SoC Boot Guide - Cyclone V SoC Development Kit Altera Corporation Send Feedback...
  • Page 5 Booting and Configuration For more information about the SD/MMC clocking options selected by Boot ROM based on CSEL pins, refer to the Booting and Configuration chapter of the Cyclone V Technical Reference Manual. Boot from QSPI When booting from QSPI, the four Preloader images are always located at the beginning of the QSPI address space, occupying a total of 256 KB.
  • Page 6 Booting and Configuration For more information about the QSPI commands and clocking options selected by Boot ROM based on CSEL pins, refer to the Booting and Configuration chapter of the Cyclone V Technical Reference Manual. Boot from NAND When booting from NAND, the Preloader images are located at the beginning of the flash. Each image has to start at NAND flash block boundary.
  • Page 7 Booting and Configuration For more information about the NAND clocking options selected by Boot ROM based on CSEL pins, refer to the Booting and Configuration chapter of the Cyclone V Technical Reference Manual. Boot from FPGA When booting from FPGA, the Boot ROM performs the following operations: •...
  • Page 8 In order to accommodate the above, the Boot ROM can be instructed to use different clocking options, through the CSEL pins. The following table presents the CSEL options available on Cyclone V, together with the actual jumper settings on the Cyclone V Development Kit, rev D:...
  • Page 9 Another example - Tweaking the Preloader so that it is made smaller. The smaller the Preloader, the less time the Boot ROM spends loading it from flash. HPS SoC Boot Guide - Cyclone V SoC Development Kit Altera Corporation Send Feedback...
  • Page 10 The Linux kernel can be made to start faster, and there is a lot of material in the Linux community on how to achieve this. For example, removing debugging capabilities and various unneeded drivers and features. Can be tweaked to achieve faster boot time. HPS SoC Boot Guide - Cyclone V SoC Development Kit Altera Corporation Send Feedback...
  • Page 11 Boot Duration Measurements This section presents various Boot time measurements taken on the Cyclone V Development Kit. Only Boot ROM and Preloader are measured. The measurements are done with the following setup: •...
  • Page 12 Since the Boot ROM is the first booting stage, the most common boot failure symptom is that not anything is happening. For example, the system does not boot, there is no activity on the UART from the Preloader (if enabled). HPS SoC Boot Guide - Cyclone V SoC Development Kit Altera Corporation Send Feedback...
  • Page 13 This prevents Boot ROM from reprogramming the PLLs and also forces it to use the lowest possible speed when communicating with the Flash device. HPS SoC Boot Guide - Cyclone V SoC Development Kit Altera Corporation Send Feedback...
  • Page 14 4 KB of OCRAM can be dumped from the debugger and it can be analyzed by Altera. This can lead to information such as “Boot ROM failed to initialize SD Card”. Most of the time, the same information can be obtained by looking at the external behavior and at the above mentioned registers.
  • Page 15 U-Boot from the ARM DS-5 AE. Since the executable is an ELF format, any other compatible debugger may be used, as well. Boot Examples This chapter presents several boot examples that can be run on the Cyclone V Development Kit: • Boot from SD/MMC - using raw and FAT partitions • Boot from QSPI •...
  • Page 16 Booting from SD/MMC – Custom Partition This example demonstrates how to boot from the SD card, with the bare-metal image stored on the same SD card custom partition as the Preloader. HPS SoC Boot Guide - Cyclone V SoC Development Kit Altera Corporation Send Feedback...
  • Page 17 115,200-8-N-1. 8. Insert the SD card on the board socket and power-cycle the board or reset the HPS by pressing the COLD reset button (S7). HPS SoC Boot Guide - Cyclone V SoC Development Kit Altera Corporation Send Feedback...
  • Page 18 To prevent the "Device Open Failed!" error message, ensure that you are operating in the following user modes: • Windows — "Administrator mode user" • Linux — "sudo mode" HPS SoC Boot Guide - Cyclone V SoC Development Kit Altera Corporation Send Feedback...
  • Page 19 9. Insert the SD card on the board socket and power-cycle the board or reset the HPS by pressing the COLD reset button (S7). The board will boot, Preloader messages will be displayed, then “Hello World” will be displayed by the bare-metal application. HPS SoC Boot Guide - Cyclone V SoC Development Kit Altera Corporation Send Feedback...
  • Page 20 1. Build the sample bare-metal application or simply use the provided file directly. hello-mkimage.bin 2. Generate a Preloader based on the GHRD provided with SoC EDS. Make sure to select the following options: HPS SoC Boot Guide - Cyclone V SoC Development Kit Altera Corporation Send Feedback...
  • Page 21 7. Power-cycle the board or reset the HPS by pressing the COLD reset button (S7). The board will boot, Preloader messages will be displayed, then “Hello World” will be displayed by the bare-metal application. HPS SoC Boot Guide - Cyclone V SoC Development Kit Altera Corporation Send Feedback...
  • Page 22 SD/MMC custom partition. If desired, the Preloader can also be configured to jump to an absolute address, that may also be located in the FPGA fabric address space. HPS SoC Boot Guide - Cyclone V SoC Development Kit Altera Corporation...
  • Page 23 Preloader. Once the Preloader hex file is obtained, the design is compiled again in order to have the FPGA memory initialized with the contents of the hex file. HPS SoC Boot Guide - Cyclone V SoC Development Kit Altera Corporation...
  • Page 24 Note: The design is already provided with this guide. It does not need to be re-created by the user. But it will need to be re-compiled if the Preloader hex file is changed. The design is based on the Altera GHRD, with a reduced number of components: • HPS - Hard Processor Instance •...
  • Page 25 AN-709 Hardware Design 2016.01.27 The following picture presents the System Contents view for the hardware design: Figure 14: System Contents View for the Hardware Design HPS SoC Boot Guide - Cyclone V SoC Development Kit Altera Corporation Send Feedback...
  • Page 26 Preloader image. The following screenshot show the memory settings that were used for this example. Note: The Preloader image is stored in the file named software/spl_bsp/preloader.hex HPS SoC Boot Guide - Cyclone V SoC Development Kit Altera Corporation Send Feedback...
  • Page 27 AN-709 Hardware Design 2016.01.27 Figure 16: On-Chip Memory Parameters HPS SoC Boot Guide - Cyclone V SoC Development Kit Altera Corporation Send Feedback...
  • Page 28 5. Convert the Preloader executable to hex file by using the following command in the Preloader folder: arm-altera-eabi-objcopy -O ihex --adjust-vma -0xc0000000 uboot-socfpga/spl/u-boot- spl preloader.hex 6. Compile the hardware design again, to take into account the newly created hex file. HPS SoC Boot Guide - Cyclone V SoC Development Kit Altera Corporation Send Feedback...
  • Page 29 • Start an Embedded Command Shell • Run the command “alt-boot-disk-util -a write -b hello-mkimage.bin -d <sd_card_drive_letter>” 9. Configure the Cyclone V board to boot from FPGA by setting the BOOTSEL jumpers like this: • BOOTSEL0 (J28): left • BOOTSEL1 (J29): right •...
  • Page 30 • Fixed incorrect spelling of "BootROM" in figures March 2015 2015.03.26 Fixed broken links. December 2014 2014.12.15 Added information for Boot Time Optimization and Boot Debug. HPS SoC Boot Guide - Cyclone V SoC Development Kit Altera Corporation Send Feedback...