Altera cyclone V Technical Reference page 185

4-42
gpio_porta_eoi
Module Instance
fpgamgrregs
Offset:
0x84C
Access:
WO
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
Reserved
gpio_porta_eoi Fields
Bit
11
fpo
10
cdp
9
nsp
Altera Corporation
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
fpo cdp
WO WO
0x0 0x0
Name
Used by software to clear an FPGA_POWER_ON
edge interrupt.
Value
0x0
0x1
Used by software to clear an CONF_DONE Pin edge
interrupt.
Value
0x0
0x1
Used by software to clear an nSTATUS Pin edge
interrupt.
Value
0x0
0x1
Base Address
0xFF706000
Bit Fields
25 24 23 22
Reserved
9 8 7 6
nsp ncp prd pre
WO WO WO WO
0x0 0x0 0x0 0x0
Description
Description
No interrupt clear
Clear interrupt
Description
No interrupt clear
Clear interrupt
Description
No interrupt clear
Clear interrupt
Register Address
0xFF70684C
21 20 19 18
5 4 3 2
prr ccd crc id
WO WO WO WO
0x0 0x0 0x0 0x0
Access
cv_5v4
2016.10.28
17 16
1 0
cd ns
WO WO 0x0
0x0
Reset
WO 0x0
WO 0x0
WO 0x0
FPGA Manager
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