Altera cyclone V Technical Reference page 48

cv_5v4
2016.10.28
Changing Values That Affect Main Clock Group PLL Lock
To change any value that affects the VCO lock of the main clock group PLL including the hardware-
managed clocks, software must put the main PLL in bypass mode, which causes all the main PLL output
clocks to be driven by the
register prior to taking the main PLL out of bypass mode.
Once a PLL is locked, changes to any PLL VCO frequency that are 20 percent or less do not cause the PLL
to lose lock. Iteratively changing the VCO frequency in increments of 20 percent or less allow a slow ramp
of the VCO base frequency without loss of lock. For example, to change a VCO frequency by 40% without
losing lock, change the frequency by 20%, then change it again by 16.7%.
Peripheral Clock Group
The peripheral clock group consists of a PLL, dividers, and clock gating. The clocks in the peripheral clock
group are derived from the peripheral PLL. The peripheral PLL can be programmed to be sourced from
the
HPS_CLK1
The FPGA fabric must be configured with an image that provides the
selecting it as the clock source. If the FPGA must be reconfigured and
by modules in the HPS, an alternate clock source must be selected prior to reconfiguring the FPGA.
Clocks that always use the peripheral PLL output clocks as the clocks source are:
•
emac0_clk
•
emac1_clk
•
usb_mp_clk
•
spi_m_clk
•
can0_clk
•
can1_clk
•
gpio_db_clk
•
h2f_user1_clk
In addition, clocks that may use the peripheral PLL output clocks as the clock source are:
•
sdmmc_clk
•
nand_clk
•
qspi_clk
•
l4_mp_clk
•
l4_sp_clk
The counter outputs from the main PLL can have their frequency further divided by external dividers.
Transitions to a different divide value occur on the fastest output clock, one clock cycle prior to the slowest
clock's rising edge. For example, the clock transitions on cycle 15 of the divide-by-16 divider for the main
C2 output and cycle 3 of the divide-by-4 divider for the C1 output.
Clock Manager
Send Feedback
clock. Software must detect PLL lock by reading the lock status
osc1_clk
pin, the pin, or the
HPS_CLK2
Changing Values That Affect Main Clock Group PLL Lock
clock provided by the FPGA fabric.
f2h_periph_ref_clk
before
f2h_periph_ref_clk
is being used
f2h_periph_ref_clk
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