Altera cyclone V Technical Reference page 169

4-26
gpio_inten
Bit
6
pre
5
prr
4
ccd
3
crc
2
id
1
cd
Altera Corporation
Name
Enables interrupt generation for PR_ERROR
Value
0x0
0x1
Enables interrupt generation for PR_READY
Value
0x0
0x1
Enables interrupt generation for CVP_CONF_DONE
Value
0x0
0x1
Enables interrupt generation for CRC_ERROR
Value
0x0
0x1
Enables interrupt generation for INIT_DONE
Value
0x0
0x1
Enables interrupt generation for CONF_DONE
Value
0x0
0x1
Description
Description
Disable Interrupt
Enable Interrupt
Description
Disable Interrupt
Enable Interrupt
Description
Disable Interrupt
Enable Interrupt
Description
Disable Interrupt
Enable Interrupt
Description
Disable Interrupt
Enable Interrupt
Description
Disable Interrupt
Enable Interrupt
cv_5v4
2016.10.28
Access Reset
RW 0x0
RW 0x0
RW 0x0
RW 0x0
RW 0x0
RW 0x0
FPGA Manager
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