Csr Interface - Altera cyclone V Technical Reference

cv_5v4
2016.10.28

CSR Interface

The CSR interface connects to the level 4 (L4) bus and operates on the
subsystem uses the CSR interface to configure the controller and PHY, for example setting the memory
timing parameter values or placing the memory in a low power state. The CSR interface also provides
access to the status registers in the controller and PHY.
FPGA-to-HPS SDRAM Interface
The FPGA-to-HPS SDRAM interface provides masters implemented in the FPGA fabric access to the
SDRAM controller subsystem in the HPS. The interface has three port types that are used to construct the
following AXI or Avalon-MM interfaces:
• Command ports—issue read and/or write commands, and for receive write acknowledge responses
• 64-bit read data ports—receive data returned from a memory read
• 64-bit write data ports—transmit write data
The FPGA-to-HPS SDRAM interface supports six command ports, allowing up to six Avalon-MM
interfaces or three AXI interfaces. Each command port can be used to implement either a read or write
command port for AXI, or be used as part of an Avalon-MM interface. The AXI and Avalon-MM
interfaces can be configured to support 32-, 64-, 128-, and 256-bit data.
Table 11-2: FPGA-to-HPS SDRAM Controller Port Types
Command
64-bit read data
64-bit write data
The FPGA-to-HPS SDRAM controller interface can be configured with the following characteristics:
• Avalon-MM interfaces and AXI interfaces can be mixed and matched as required by the fabric logic,
within the bounds of the number of ports provided to the fabric.
• Because the AXI protocol allows simultaneous read and write commands to be issued, two SDRAM
control ports are required to form an AXI interface.
• Because the data ports are natively 64-bit, they must be combined if wider data paths are required for
the interface.
• Each Avalon-MM or AXI interface of the FPGA-to-HPS SDRAM interface operates on an independent
clock domain.
• The FPGA-to-HPS SDRAM interfaces are configured during FPGA configuration.
The following table shows the number of ports needed to configure different bus protocols, based on type
and data width.
Table 11-3: FPGA-to-HPS SDRAM Port Utilization
Bus Protocol
32- or 64-bit AXI
SDRAM Controller Subsystem
Send Feedback
Port Type
Command Ports
Available Number of Ports
Read Data Ports
2 1
CSR Interface
clock domain. The MPU
l4_sp_clk
6
4
4
Write Data Ports
1
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