Dma Controller - Altera cyclone V Technical Reference

5-4

DMA Controller

you must program both the peripheral's CSR and its corresponding CSR in the System Manager. This
section describes how to configure the system manager CS for each module.
DMA Controller
The security state of the DMA controller is controlled by the manager thread security (
interrupt security (
The
periph_ns
Note: The
Related Information
• DMA Controller
• System Manager Address Map and Register Definitions
NAND Flash Controller
The bootstrap control register (
controller after reset. The NAND flash controller samples the bootstrap control register bits when it comes
out of reset.
The following
• Bootstrap inhibit initialization bit (
when coming out of reset, and allows software to program all registers pertaining to device parameters
such as page size and width.
• Bootstrap 512-byte device bit (
device with a 512-byte page size is connected to the system.
• Bootstrap inhibit load block 0 page 0 bit (
loading page 0 of block 0 of the NAND flash device during the initialization procedure.
• Bootstrap two row address cycles bit (
row address cycles are required instead of the default three row address cycles.
You can use the system manager's
• ARPROT
• AWPROT
• ARDOMAIN
• AWDOMAIN
• ARCACHE
• AWCACHE
These bits define the cache attributes for the master transactions of the DMA engine in the NAND
controller.
Note: Register bits must be accessed only when the master interface is guaranteed to be in an inactive
state.
Related Information
NAND Flash Controller
•
System Manager Address Map and Register Definitions
•
Altera Corporation
) bits of the DMA register.
irq_ns
register bits determine if a peripheral request interface is secure or non-secure.
register bits must be configured before the DMA is released from global reset.
periph_ns
on page 16-1
nand_bootstrap
register bits control configuration of the NAND flash controller:
nand_bootstrap
page512
nanad_l3master
on page 13-1
on page 5-9
) modifies the default behavior of the NAND flash
)—inhibits the NAND flash controller from initializing
noinit
)—informs the NAND flash controller that a NAND flash
)—inhibits the NAND flash controller from
noloadb0p0
)—informs the NAND flash controller that only two
tworowaddr
register to control the following signals:
on page 5-9
cv_5v4
2016.10.28
) and
mgr_ns
System Manager
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