Flash Memory Controllers - Altera cyclone V Technical Reference

Hard processor system
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Flash Memory Controllers

Related Information
On-Chip Memory
Booting and Configuration
Flash Memory Controllers
NAND Flash Controller
The NAND flash controller is based on the Cadence
offers the following functionality and features:
• Supports one x8 NAND flash device
• Supports Open NAND Flash Interface (ONFI) 1.0
• Supports NAND flash memories from Hynix, Samsung, Toshiba, Micron, and ST Micro
• Supports programmable 512 byte (4-, 8-, or 16-bit correction) or 1024 byte (24-bit correction) ECC
sector size
• Supports pipeline read-ahead and write commands for enhanced read/write throughput
• Supports devices with 32, 64, 128, 256, 384, or 512 pages per block
• Supports multiplane devices
• Supports page sizes of 512 bytes, 2 kilobytes (KB), 4 KB, or 8 KB
• Supports single-level cell (SLC) and multi-level cell (MLC) devices with programmable correction
capabilities
• Provides internal DMA
• Provides programmable access timing
Related Information
NAND Flash Controller
Quad SPI Flash Controller
The quad SPI flash controller is based on the Cadence Quad SPI Flash Controller and offers the following
features:
• Supports SPIx1, SPIx2, or SPIx4 (Quad SPI) serial NOR flash devices
• Supports direct access and indirect access modes
• Supports single, dual, and quad I/O instructions
• Support up to four chip selects
• Programmable write-protected regions
• Programmable delays between transactions
• Programmable device sizes
• Support eXecute-In-Place (XIP) mode
• Programmable baud rate generator to generate device clocks
Related Information
Quad SPI Flash Controller
Altera Corporation
on page 12-1
on page 30-1
on page 13-1
on page 15-1
Design IP
NAND Flash Memory Controller and
®
®
Introduction to the Hard Processor System
cv_5v4
2016.10.28
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