Altera cyclone V Technical Reference page 755

cv_5v4
2016.10.28
User Notification of ECC Errors
When an ECC error occurs, an interrupt signal notifies the MPU subsystem, and the ECC error
information is stored in the status registers. The memory controller provides interrupts for single-bit and
double-bit errors.
The status of interrupts and errors are recorded in status registers, as follows:
• The
dramsts
• The
dramintr
• The
sbecount
• The
dbecount
• The
erraddr
For a 32-bit interface, ECC is calculated across a span of 8 bytes, meaning the error address is a multiple of
8 bytes (4-bytes*2 burst length). To find the byte address of the word that contains the error, you must
multiply the value in the
Related Information
Cortex-A9 Microprocessor Unit Subsystem
Information about ECC error interrupts
Interleaving Options
The controller supports the following address-interleaving options:
• Non-interleaved
• Bank interleave without chip select interleave
• Bank interleave with chip select interleave
The following interleaving examples use 512 megabits (Mb) x 16 DDR3 chips and are documented as byte
addresses. For RAMs with smaller address fields, the order of the fields stays the same but the widths may
change.
Non-interleaved
RAM mapping is non-interleaved.
SDRAM Controller Subsystem
Send Feedback
register records interrupt status.
register records interrupt masks.
register records the single-bit error count.
register records the double-bit error count.
register records the address of the most recent error.
register by 8.
erraddr
User Notification of ECC Errors
on page 9-1
11-17
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