Altera cyclone V Technical Reference page 890

cv_5v4
2016.10.28
31 30
15 14
rdwr_en_lo_cnt Fields
Bit
4:0
value
rdwr_en_hi_cnt
Read/Write Enable high pulse width
Module Instance
nandregs
Offset:
0x200
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
NAND Flash Controller
Send Feedback
29 28 27 26
13 12 11 10
Reserved
Name
Number of nand_mp_clk cycles that read or write
enable will kept low to meet the min Trp/Twp
parameter of the device. The value in this register plus
rdwr_en_hi_cnt register value should meet the min
cycle time of the device connected. The default value
is calculated assuming the max nand_mp_clk time
period of 4ns to work with ONFI Mode 0 mode of
100ns device cycle time. This assumes a 1x/4x
clocking scheme.
0xFFB80000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Reserved
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Description
Base Address
Bit Fields
25 24 23 22
Reserved
9 8 7 6
rdwr_en_hi_cnt
21 20 19 18
5 4 3 2
value
RW 0x12
Access
Register Address
0xFFB80200
21 20 19 18
5 4 3 2
value
RW 0xC
13-69
17 16
1 0
Reset
RW 0x12
17 16
1 0
Altera Corporation