Altera cyclone V Technical Reference page 18

1-2
Introduction to the Hard Processor System
The HPS incorporates third-party intellectual property (IP) from several vendors.
The dual-processor HPS supports symmetric (SMP) and asymmetric (AMP) multiprocessing.
The FPGA portion of the device contains:
• FPGA fabric
• Control block (CB)
• PLLs
• High-speed serial interface (HSSI) transceivers, depending on the device variant
• Hard PCI Express
• Hard memory controllers
The HPS and FPGA communicate with each other through bus interfaces that bridge the two distinct
portions. On a power-on reset, the HPS can boot from multiple sources, including the FPGA fabric and
external flash. The FPGA can be configured through the HPS or an externally supported device.
The HPS and FPGA portions of the device each have their own pins. Pins are not freely shared between
the HPS and the FPGA fabric. The HPS I/O pins are configured by boot software executed by the MPU in
the HPS. Software executing on the HPS accesses control registers in the system manager to assign HPS
I/O pins to the available HPS modules. The FPGA I/O pins are configured by an FPGA configuration
image through the HPS or any external source supported by the device.
The MPU subsystem can boot from flash devices connected to the HPS pins. When the FPGA portion is
configured by an external source, the MPU subsystem can boot from flash memory devices available to the
FPGA portion of the device.
The HPS and FPGA portions of the device have separate external power supplies and independently
power on. You can power on the HPS without powering on the FPGA portion of the device. However, to
power on the FPGA portion, the HPS must already be on or powered at the same time as the FPGA
portion. You can also turn off the FPGA portion of the device while leaving the HPS power on.
Table 1-1: Valid SoC Power Modes
HPS
Off
Off
On
On
Related Information
• Booting and Configuration
• Cyclone V Device Datasheet
Altera Corporation
(PCI-e) controllers
®
FPGA
Off
On
Off
On
on page 30-1
Valid?
Yes
No
Yes
Yes
Introduction to the Hard Processor System
cv_5v4
2016.10.28
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