Altera cyclone V Technical Reference page 970

14-24
Polling the CCS
bit is set to 1 in the ATA control register), that is, the CCS expected bit (
is set to 0. If the command expects the CCS, the P-bit is driven only after receiving the CCS.
Polling the CCS
CE-ATA card devices generate the CCS to notify the host controller of the normal ATA command
completion or ATA command termination. After receiving the response from the card, the command path
state machine performs the functions illustrated in the following figure according to
†
values.
Figure 14-7: CE‑ATA Command Path State Machine
okay_to_send_ccsd
The above figure illustrates:
• Response end bit state—The state machine receives the end bit of the response from the card device. If
the
ccs_expected
• Wait CCS—The state machine waits for the CCS from the CE-ATA card device. While waiting for the
CCS, the following events can happen:
1. Software sets the send CCSD bit (
and to send the CCSD pattern on the command line.
2. Receive the CCS on the CMD line.
• Send CCSD command—Sends the CCSD pattern (0b00001) on the CMD line.
CCS Detection and Interrupt to Host Processor
If the
ccs_expected
by setting the data transfer over bit (
if this interrupt is not masked.
For the RW_MULTIPLE_BLOCK commands, if the CE-ATA card device interrupts are disabled (the
bit is set to 1 in the ATA control register)— that is, the
there are no CCSs from the card. When the data transfer is over—that is, when the requested number of
bytes are transferred—the
Altera Corporation
ccs_expected = 1
cmd_in = 0
wait_CCS
counter_zero
send_CCSD
bit of the register is set to 1, the state machine enters the wait CCS state.
cmd
bit in the register is set to 1, the CCS from the CE-ATA card device is indicated
cmd
dto
†
bit in the
dto
†
Response
End Bit
ccs_expected = 0
wait_tncc
†
) in the
send_ccsd ctrl
†
†
) in the register. The controller generates a DTO interrupt
rintsts
ccs_expected
register is set to 1.
rintsts
) in the
ccs_expected
cmd
Transmit
CMD12
Command
send_auto_stop_ccsd
Idle
register, indicating not to wait for CCS
†
bit is set to 0 in the
†
cv_5v4
2016.10.28
register
cmd
†
register bit
†
nIEN
register—
cmd
SD/MMC Controller
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