Altera cyclone V Technical Reference page 365

cv_5v4
2016.10.28
GPLINMUX65 Fields
Bit
0
sel
GPLINMUX66
Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects the input signal for GPIO/
LoanIO 66. Only reset by a cold reset (ignores warm reset). NOTE: These registers should not be modified
after IO configuration.There is no support for dynamically changing the Pin Mux selections.
Module Instance
sysmgr
Offset:
0x5C0
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
GPLINMUX66 Fields
Bit
0
sel
GPLINMUX67
Some GPIO/LoanIO inputs can be driven by multiple pins. This register selects the input signal for GPIO/
LoanIO 67. Only reset by a cold reset (ignores warm reset). NOTE: These registers should not be modified
after IO configuration.There is no support for dynamically changing the Pin Mux selections.
System Manager
Send Feedback
Name
Select source for GPIO/LoanIO 65. 0 : Source for
GPIO/LoanIO 65 is GENERALIO17. 1 : Source for
GPIO/LoanIO 65 is GENERALIO26.
0xFFD08000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Name
Select source for GPIO/LoanIO 66. 0 : Source for
GPIO/LoanIO 66 is GENERALIO18. 1 : Source for
GPIO/LoanIO 66 is GENERALIO27.
Description
Base Address
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Reserved
Description
GPLINMUX66
Access
Register Address
0xFFD085C0
21 20 19 18
5 4 3 2
Access
5-171
Reset
RW 0x0
17 16
1 0
sel
RW 0x0
Reset
RW 0x0
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