Altera cyclone V Technical Reference page 69

2-32
stat
31 30
15 14
dbctrl Fields
Bit
1
ensfmdwr
0
stayosc1
stat
Provides status of Hardware Managed Clock transition State Machine.
Module Instance
clkmgr
Offset:
0x14
Access:
RO
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
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29 28 27 26
13 12 11 10
Name
When this bit is set the debug clocks will be affected
by the assertion of Safe Mode on a warm reset if Stay
OSC1 is not set. When this bit is clear the debug
clocks will not be affected by the assertion of Safe
Mode on a warm reset. If Debug Clocks are in Safe
Mode they are taken out of Safe Mode when the Safe
Mode bit is cleared independent of this bit. The reset
value of this bit is applied on a cold reset; warm reset
has no effect on this bit.
When this bit is set the debug root clock (Main PLL
C2 output) will always be bypassed to the EOSC1_clk
independent of any other clock manager settings.
When clear the debug source will be a function of
register settings in the clock manager. Clocks affected
by this bit are dbg_at_clk, dbg_clk, dbg_trace_clk,
and dbg_timer_clk. The reset value for this bit is
applied on a cold reset. Warm reset has no effect on
this bit.
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Reserved
Description
Base Address
0xFFD04000
21 20 19 18
5 4 3 2
Access
Register Address
0xFFD04014
cv_5v4
2016.10.28
17 16
1 0
ensfm stayosc1
dwr
RW 0x1
RW
0x1
Reset
RW 0x1
RW 0x1
Clock Manager
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