Altera cyclone V Technical Reference page 174

cv_5v4
2016.10.28
Offset:
0x838
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
Reserved
gpio_inttype_level Fields
Bit
11
fpo
10
cdp
9
nsp
FPGA Manager
Send Feedback
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
fpo cdp
RW RW
0x0 0x0
Name
Controls whether the level of FPGA_POWER_ON or
an edge on FPGA_POWER_ON generates an
interrupt.
0x0
0x1
Controls whether the level of CONF_DONE Pin or
an edge on CONF_DONE Pin generates an interrupt.
0x0
0x1
Controls whether the level of nSTATUS Pin or an
edge on nSTATUS Pin generates an interrupt.
0x0
0x1
Bit Fields
25 24 23 22
Reserved
9 8 7 6
nsp ncp prd pre
RW RW RW RW
0x0 0x0 0x0 0x0
Description
Value Description
Level-sensitive
Edge-sensitive
Value Description
Level-sensitive
Edge-sensitive
Value Description
Level-sensitive
Edge-sensitive
gpio_inttype_level
21 20 19 18
5 4 3 2
prr ccd crc id
RW RW RW RW
0x0 0x0 0x0 0x0
Access
4-31
17 16
1 0
cd ns
RW RW 0x0
0x0
Reset
RW 0x0
RW 0x0
RW 0x0
Altera Corporation