Sdram Power Management - Altera cyclone V Technical Reference

11-24

SDRAM Power Management

Table 11-10: Result for a Sample Set of Transactions
Operation
Read CPU
Write CPU
Write L3 attached masters 605, 028, 350
Read L3 attached masters 4096
Write CPU
Write L3 attached masters 605, 028, 350
Note: If a master is using the Accelerator Coherency Port (ACP) to maintain cache coherency with the
Cortex-A9 MPCore processor, then the address ranges in the rules of the memory protection table
should be made mutually exclusive, such that the secure and non-secure regions do not overlap and
any area that is shared is part of the non-secure region. This configuration prevents coherency
issues from occurring.
SDRAM Power Management
The SDRAM controller subsystem supports the following power saving features in the SDRAM:
• Partial array self-refresh (PASR)
• Power down
• Deep power down for LPDDR2
To enable self-refresh for the memories of one or both chip selects, program the
sefrfshmask
Power-saving mode initiates either due to a user command or from inactivity. The number of idle clock
cycles after which a memory can be put into power-down mode is programmed through the
field of the
cles
Power-down mode forces the SDRAM burst-scheduling bank-management logic to close all banks and
issue the power down command. The SDRAM automatically reactivates when an active SDRAM
command is received.
Altera Corporation
Source Address Accesses
4096
536, 870, 912
536, 870, 912
bit in the register.
lowpwreq
register.
lowpwrtiming
Security Result
Access
Type
secure Allow Matches rule 1.
secure Allow Matches rule 1.
secure Fail Does not match rule 1 (out
of range of the address field)
, does not match rule 2
(protection bit incorrect).
non- Fail Does not match rule 1
secure (AxPROT signal value
wrong), does not match
rule 2 (not in address
range).
non- Allow Matches rule 2.
secure
non- Allow Matches rule 2.
secure
cv_5v4
2016.10.28
Comments
bit and the
selfshreq
autopdycy-
SDRAM Controller Subsystem
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