Altera cyclone V Technical Reference page 216

5-22
System Manager Module Address Map
Register
GPLMUX55 on page 5-
218
GPLMUX56 on page 5-
219
GPLMUX57 on page 5-
220
GPLMUX58 on page 5-
221
GPLMUX59 on page 5-
222
GPLMUX60 on page 5-
222
GPLMUX61 on page 5-
223
GPLMUX62 on page 5-
224
GPLMUX63 on page 5-
225
GPLMUX64 on page 5-
226
GPLMUX65 on page 5-
226
GPLMUX66 on page 5-
227
GPLMUX67 on page 5-
228
GPLMUX68 on page 5-
229
GPLMUX69 on page 5-
230
GPLMUX70 on page 5-
230
NANDUSEFPGA
5-231
RGMII1USEFPGA
5-232
I2C0USEFPGA
5-232
RGMII0USEFPGA
5-233
Altera Corporation
Offset
0x6B0
0x6B4
0x6B8
0x6BC
0x6C0
0x6C4
0x6C8
0x6CC
0x6D0
0x6D4
0x6D8
0x6DC
0x6E0
0x6E4
0x6E8
0x6EC
on page 0x6F0
on page 0x6F8
on page 0x704
on page 0x714
Width Acces Reset Value
s
32 RW 0x0
32 RW 0x0
32 RW 0x0
32 RW 0x0
32 RW 0x0
32 RW 0x0
32 RW 0x0
32 RW 0x0
32 RW 0x0
32 RW 0x0
32 RW 0x0
32 RW 0x0
32 RW 0x0
32 RW 0x0
32 RW 0x0
32 RW 0x0
32 RW 0x0
32 RW 0x0
32 RW 0x0
32 RW 0x0
Description
GPIO/LoanIO 55 Output/Output
Enable Mux Selection Register
GPIO/LoanIO 56 Output/Output
Enable Mux Selection Register
GPIO/LoanIO 57 Output/Output
Enable Mux Selection Register
GPIO/LoanIO 58 Output/Output
Enable Mux Selection Register
GPIO/LoanIO 59 Output/Output
Enable Mux Selection Register
GPIO/LoanIO 60 Output/Output
Enable Mux Selection Register
GPIO/LoanIO 61 Output/Output
Enable Mux Selection Register
GPIO/LoanIO 62 Output/Output
Enable Mux Selection Register
GPIO/LoanIO 63 Output/Output
Enable Mux Selection Register
GPIO/LoanIO 64 Output/Output
Enable Mux Selection Register
GPIO/LoanIO 65 Output/Output
Enable Mux Selection Register
GPIO/LoanIO 66 Output/Output
Enable Mux Selection Register
GPIO/LoanIO 67 Output/Output
Enable Mux Selection Register
GPIO/LoanIO 68 Output/Output
Enable Mux Selection Register
GPIO/LoanIO 69 Output/Output
Enable Mux Selection Register
GPIO/LoanIO 70 Output/Output
Enable Mux Selection Register
Select source for NAND signals
(HPS Pins or FPGA Interface)
Select source for RGMII1 signals
(HPS Pins or FPGA Interface)
Select source for I2C0 signals
(HPS Pins or FPGA Interface)
Select source for RGMII0 signals
(HPS Pins or FPGA Interface)
System Manager
Send Feedback
cv_5v4
2016.10.28