Altera cyclone V Technical Reference page 700

9-64
Single Event Upset Protection
EPFRCVDS1
IPFALLOC
IRHIT
IRREQ
SPNIDEN
SRCONFS0
SRCONFS1
SRRCVDS0
SRRCVDS1
WA
In addition, the L2 cache events can be captured and timestamped using dedicated debugging circuitry.
Related Information
ARM Infocenter
For more information about L2 event capture, refer to the Debug chapter of the Cortex-A9 MPCore
Technical Reference Manual, available on the ARM Infocenter website.
Single Event Upset Protection
The L2 cache has the option of using ECCs to protect against Single Event Upset (SEU) errors in the cache
RAM.
The L2 cache has two types of protection:
• The L2 cache tag RAMs are protected by parity.
• The L2 cache data RAMs are protected using single error correction, double error detection (SECDED)
ECC Hamming code.
Enabling ECCs does not affect the performance of the L2 cache. The ECC bits are calculated only for
writes to the data RAM that are 64 bits wide (8 bytes, or one-quarter of the cache line length). The ECC
logic does not perform a read-modify-write when calculating the ECC bits.
Altera Corporation
Event Description
Prefetch hint received by slave port S1.
Allocation of a prefetch generated by L2 cache
controller into the L2 cache.
Instruction read hit in the L2 cache.
Instruction read lookup to the L2 cache.
Subsequently results in a hit or miss.
Secure privileged non-invasive debug enable.
Speculative read confirmed in slave port S0.
Speculative read confirmed in slave port S1.
Speculative read received by slave port S0.
Speculative read received by slave port S1.
Allocation into the L2 cache caused by a write (with
write-allocate attribute) miss.
Cortex-A9 Microprocessor Unit Subsystem
cv_5v4
2016.10.28
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