Altera cyclone V Technical Reference page 71

2-34
vco
dbgatclk
on page 2-39
Contains settings that control clock dbg_base_clk generated from the C2 output of the Main PLL. Only
reset by a cold reset.
mainqspiclk
Contains settings that control clock main_qspi_clk generated from the C3 output of the Main PLL. Only
reset by a cold reset.
mainnandsdmmcclk
Contains settings that control clock main_nand_sdmmc_clk generated from the C4 output of the Main
PLL. Only reset by a cold reset.
cfgs2fuser0clk
Contains settings that control clock cfg_s2f_user0_clk generated from the C5 output of the Main PLL.
Qsys and user documenation refer to cfg_s2f_user0_clk as cfg_h2f_user0_clk. Only reset by a cold reset.
en on page 2-41
Contains fields that control clock enables for clocks derived from the Main PLL. 1: The clock is enabled. 0:
The clock is disabled. Fields are only reset by a cold reset.
maindiv on page 2-42
Contains fields that control clock dividers for main clocks derived from the Main PLL Fields are only reset
by a cold reset.
dbgdiv on page 2-44
Contains fields that control clock dividers for debug clocks derived from the Main PLL Fields are only
reset by a cold reset.
tracediv on page 2-45
Contains a field that controls the clock divider for the debug trace clock derived from the Main PLL Only
reset by a cold reset.
l4src
on page 2-46
Contains fields that select the clock source for L4 MP and SP APB interconnect Fields are only reset by a
cold reset.
stat
on page 2-47
Contains Output Clock Counter Reset acknowledge status.
vco
Contains settings that control the Main PLL VCO. The VCO output frequency is the input frequency
multiplied by the numerator (M+1) and divided by the denominator (N+1). The VCO input clock source
is always eosc1_clk. Fields are only reset by a cold reset.
Module Instance
clkmgr
Offset:
0x40
Access:
RW
Altera Corporation
on page 2-39
on page 2-40
on page 2-41
0xFFD04000
Base Address
2016.10.28
Register Address
0xFFD04040
Clock Manager
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cv_5v4