Altera cyclone V Technical Reference page 711

2016.10.28
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CoreSight systems provide all the infrastructure you require to debug, monitor, and optimize the perform‐
ance of a complete HPS design. CoreSight technology addresses the requirement for a multicore debug
and trace solution with high bandwidth for whole systems beyond the processor core.
CoreSight technology provides the following features:
• Cross-trigger support between SoC subsystems
• High data compression
• Multi-source trace in a single stream
• Standard programming models for standard tool support
The hard processor system (HPS) debug infrastructure provides visibility and control of the HPS modules,
the ARM Cortex-A9 microprocessor unit (MPU) subsystem, and user logic implemented in the FPGA
fabric. The debug system design incorporates ARM CoreSight
Details of the ARM CoreSight debug components can be viewed by clicking on the following related
information links:
Related Information
• Debug Access Port
System Trace Macrocell
•
Trace Funnel
•
Embedded Trace FIFO
•
• AMBA Trace Bus Replicator
• Embedded Trace Router
Trace Port Interface Unit
•
Embedded Cross Trigger System
•
• Program Trace Macrocell
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are trademarks of Intel Corporation in the US and/or other countries. Other marks and brands may be claimed as the property of others. Intel warrants
performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make
changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any
information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of
device specifications before relying on any published information and before placing orders for products or services.
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