Altera cyclone V Technical Reference page 664

9-28
AxUSER and AxCACHE Attributes
Coherent Memory, Snoop Control Unit, and Accelerator Coherency Port
•
• Cyclone V SX, ST and SE SoC Device Errata
AxUSER and AxCACHE Attributes
ARUSER[0] and AWUSER[0] Bits
The table below shows how the
ARUSER[0] applies to read transactions, and AWUSER[0] applies to write transactions.
Table 9-4: ARUSER[0] or AWUSER[0] Sideband Signal Information
ARUSER[0]
Other
AxUSER
Note: Except for the FPGA-to-HPS masters, the ACP ID mapper provides the
masters.
ARCACHE[4:0] and AWCACHE[4:0] Bits
The Cortex-A9 MPU only interprets
are forwarded to the L2 cache.
access. If
AxCACHE[1]
coherent. All ACP requests with
Table 9-5: ARUSER[0] or AWUSER[0] Sideband Signal Information
or
ARCACHE[1]
1
0
Related Information
Control of the AXI User Sideband Signals
Cache Coherency for ACP Shared Requests
When a shared access is received on the ACP, caches are checked for coherency of the requested address. A
shared access occurs when two masters access the same memory space.
This coherency check is performed by the SCU. If a cache hit occurs during a write access, the affected
cache lines are cleaned and invalidated. This event may cause an eviction from the L1 cache to be sent to
L2 memory if the L1 cache line is dirty. Once the invalidation and possible eviction is completed, the ACP
write request is written to L2 memory. If an eviction was executed from L1 cache, then two consecutive
writes to L2 memory occur over the AXI bus: the write from the eviction and the write from the ACP.
For a cache hit during a read access, the L1 cache line is provided by the CPU and is returned to the ACP.
Altera Corporation
AxUSER[0]
or
AWUSER[0]
1
0
bits from the ACP are not interpreted by the SCU but are forwarded to the L2 cache.
AxCACHE[1]
=0x1, (normal memory) and
AxCACHE[1]
AWCACHE[1]
bit determines whether a request is shared or non-shared.
and
ARCACHE[1] AWCACHE[1]
is used in combination with
AxUSER[0]
=0x0 or
AxUSER[0]
or
ARUSER[0] AWUSER[0]
1
0
on page 9-36
on page 9-26
Sideband Signal Information
Shared request
Non-shared request
signals for all other
AxUSER
from ACP requests. All other attributes
to detect a coherent
AxUSER[0]
=0x1, then the access is considered
=0x0 are seen as non-coherent requests.
Access Type
Coherent request
Non-coherent request
Cortex-A9 Microprocessor Unit Subsystem
cv_5v4
2016.10.28
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