Altera cyclone V Technical Reference page 900

Hard processor system
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cv_5v4
2016.10.28
onfi_device_features
Features supported by the connected ONFI device
onfi_optional_commands
Optional commands supported by the connected ONFI device
onfi_timing_mode
Asynchronous Timing modes supported by the connected ONFI device
onfi_pgm_cache_timing_mode
Asynchronous Program Cache Timing modes supported by the connected ONFI device
onfi_device_no_of_luns
Indicates if the device is an ONFI compliant device and the number of LUNS present in the device
onfi_device_no_of_blocks_per_lun_l
Lower bits of number of blocks per LUN present in the ONFI complaint device.
onfi_device_no_of_blocks_per_lun_u
Upper bits of number of blocks per LUN present in the ONFI complaint device.
features
on page 13-90
Shows Available hardware features or attributes
manufacturer_id
Module Instance
nandregs
Offset:
0x300
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31
30
15
14
NAND Flash Controller
Send Feedback
on page 13-84
on page 13-85
on page 13-86
on page 13-87
on page 13-87
0xFFB80000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29
28
27
26
13
12
11
10
Reserved
on page 13-88
on page 13-89
Base Address
Bit Fields
25
24
23
22
Reserved
9
8
7
6
manufacturer_id
Register Address
0xFFB80300
21
20
19
18
5
4
3
2
value
RW 0x0
13-79
17
16
1
0
Altera Corporation

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