Altera cyclone V Technical Reference page 747

cv_5v4
2016.10.28
Arbiter
The arbiter determines the order in which requests are passed to the memory device. When the arbiter
receives a single request, that request is passed immediately. When multiple requests are received, the
arbiter uses arbitration rules to determine the order to pass requests to the memory device.
Related Information
Memory Controller Architecture
For more information, refer to the SDRAM Controller Block diagram.
Rank Timer
The rank timer performs the following functions:
• Maintains rank-specific timing information
• Ensures that only four activates occur within a specified timing window
• Manages the read-to-write and write-to-read bus turnaround time
• Manages the time-to-activate delay between different banks
Related Information
Memory Controller Architecture
For more information, refer to the SDRAM Controller Block diagram.
Write Data Buffer
The write data buffer receives write data from the MPFE and passes the data to the PHY, on approval of
the write request.
Related Information
Memory Controller Architecture
For more information, refer to the SDRAM Controller Block diagram.
ECC Block
The ECC block consists of an encoder and a decoder-corrector, which can detect and correct single-bit
errors, and detect double-bit errors. The ECC block can correct single- bit errors and detect double-bit
errors resulting from noise or other impairments during data transmission.
Note: The level of ECC support is package dependent.
Related Information
• Memory Controller Architecture
For more information, refer to the SDRAM Controller Block diagram.
External Memory Interfaces in Cyclone V Devices
•
AFI Interface
The AFI interface provides communication between the controller and the PHY.
Related Information
Memory Controller Architecture
For more information, refer to the SDRAM Controller Block diagram.
SDRAM Controller Subsystem
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Arbiter
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