Altera cyclone V Technical Reference page 657

cv_5v4
2016.10.28
GIC Source Block
Interrupt
Number
150 EMAC0
151 EMAC0
152 EMAC1
153 EMAC1
154 EMAC1
155 EMAC1
156 EMAC1
157 USB0
158 USB0
159 USB0
160 USB1
161 USB1
162 USB1
163 CAN0
164 CAN0
165 CAN0
166 CAN0
167 CAN1
168 CAN1
169 CAN1
170 CAN1
Cortex-A9 Microprocessor Unit Subsystem
Send Feedback
Interrupt Name
emac0_rx_ecc_corrected_IRQ
emac0_rx_ecc_uncorrected_
IRQ
emac1_IRQ
emac1_tx_ecc_corrected_IRQ
emac1_tx_ecc_uncorrected_
IRQ
emac1_rx_ecc_corrected_IRQ
emac1_rx_ecc_uncorrected_
IRQ
usb0_IRQ
usb0_ecc_corrected_IRQ
usb0_ecc_uncorrected_IRQ
usb1_IRQ
usb1_ecc_corrected_IRQ
usb1_ecc_uncorrected_IRQ
can0_sts_IRQ
can0_mo_IRQ
can0_ecc_corrected_IRQ
can0_ecc_uncorrected_IRQ
can1_sts_IRQ
can1_mo_IRQ
can1_ecc_corrected_IRQ
can1_ecc_uncorrected_IRQ
GIC Interrupt Map for the Cyclone V SoC HPS
Combined Interrupts
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—
This interrupt combines:
and .
intr_o lpi_intr_o
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—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
9-21
Triggering
Level
Level
Level
sbd_
Level
Level
Level
Level
Level
Level
Level
Level
Level
Level
Level
Level
Level
Level
Level
Level
Level
Level
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