Interrupt And Error Handling - Altera cyclone V Technical Reference

cv_5v4
2016.10.28

Interrupt and Error Handling

This section describes how to use interrupts to handle errors. On power-on or reset, interrupts are
disabled (the
register default is 0). The controller error handling includes the following types of errors:
intmask
• Response and data timeout errors—For response time-outs, the host software can retry the command.
For data time-outs, the controller has not received the data start bit from the card, so software can
either retry the whole data transfer again or retry from a specified block onwards. By reading the
contents of the
†
(read).
• Response errors—Set to 1 when an error is received during response reception. If the response received
is invalid, the software can retry the command.
• Data errors—Set to 1 when a data receive error occurs. Examples of data receive errors:
• Data CRC
• Start bit not found
• End bit not found
These errors can be occur on any block. On receipt of an error, the software can issue an SD/SDIO
STOP or SEND_IF_COND command, and retry the command for either the whole data or partial
†
data.
• Hardware locked error—Set to 1 when the controller cannot load a command issued by software.
When software sets the
If the command buffer already contains a command, this error is raised, and the new command is
discarded, requiring the software to reload the command.
• FIFO buffer underrun/overrun error—If the FIFO buffer is full and software tries to write data to the
FIFO buffer, an overrun error is set. Conversely, if the FIFO buffer is empty and the software tries to
read data from the FIFO buffer, an underrun error is set. Before reading or writing data in the FIFO
buffer, the software must read the FIFO buffer empty bit (
(
fifo_full
• Data starvation by host timeout—This condition occurs when software does not service the FIFO
buffer fast enough to keep up with the controller. Under this condition and when a read transfer is in
process, the software must read data from the FIFO buffer, which creates space for further data
reception. When a transmit operation is in process, the software must write data to fill the FIFO buffer
so that the controller can write the data to the card.
• CE-ATA errors
• CRC error on command—If a CRC error is detected for a command, the CE-ATA card device does not
send a response, and a response timeout is expected from the controller. The ATA layer is notified that
an MMC transport layer error occurred.
SD/MMC Controller
Send Feedback
bit in the
int_enable ctrl
register later, the software can decide how many bytes remain to be copied
tcbcnt
†
†
†
start_cmd
) in the register.
status
†
register is set to 0), and all the interrupts are masked (the
†
bit in the register to 1, the controller tries to load the command.
cmd
†
fifo_empty
†
†
Interrupt and Error Handling
†
) or FIFO buffer full bit
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