Ethernet Mac Address Map And Register Definitions - Altera cyclone V Technical Reference

17-72

Ethernet MAC Address Map and Register Definitions

example, to control the PPS), then the interrupt generation is overwritten with the new mode and new
programmed Target Time register value.
Ethernet MAC Address Map and Register Definitions
The address map and register definitions pertain to the following modules:
• EMAC Module 0
• EMAC Module 1
Related Information
Introduction to the Hard Processor System
EMAC Module Address Map
Registers in the EMAC module.
Module Instance
emac0
emac1
GMAC Register Group
Register
MAC_Configuration
page 17-137
MAC_Frame_Filter
page 17-145
GMII_Address
17-151
GMII_Data on page 17-
153
Flow_Control
17-154
VLAN_Tag on page 17-
157
Version on page 17-
159
Debug on page 17-159
LPI_Control_Status
page 17-163
LPI_Timers_Control
page 17-166
Altera Corporation
Offset
on 0x0
on 0x4
on page 0x10
0x14
on page 0x18
0x1C
0x20
0x24
on 0x30
on 0x34
on page 1-1
0xFF700000
0xFF702000
Width Acces Reset Value
s
32 RW 0x0
32 RW 0x0
32 RW 0x0
32 RW 0x0
32 RW 0x0
32 RW 0x0
32 RO 0x1037
32 RO 0x0
32 RW 0x0
32 RW 0x3E80000
Base Address
Description
Register 0 (MAC Configuration
Register)
Register 1 (MAC Frame Filter)
Register 4 (GMII Address
Register)
Register 5 (GMII Data Register)
Register 6 (Flow Control Register)
Register 7 (VLAN Tag Register)
Register 8 (Version Register)
Register 9 (Debug Register)
Register 12 (LPI Control and
Status Register)
Register 13 (LPI Timers Control
Register)
Ethernet Media Access Controller
cv_5v4
2016.10.28
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