Interrupts - Altera cyclone V Technical Reference

cv_5v4
2016.10.28
interface type and all other corresponding EMAC settings in the System Manager have been configured.
For details about reset registers, refer to the "Module Reset Signals" section in the Reset Manager chapter.
For more information about EMAC configuration in the System Manager, refer to the "System Level
EMAC Configuration Registers" section.
Related Information
• System Level EMAC Configuration Registers
Module Reset Signals
•
For more information about reset registers refer to this section in the Reset Manager chapter.

Interrupts

Interrupts are generated as a result of specific events in the EMAC and external PHY device. The interrupt
status register indicates all conditions which may trigger an interrupt and the interrupt enable register
determines which interrupts can propagate.
Ethernet MAC Programming Model
The initialization and configuration of the EMAC and its interface is a multi-step process that includes
system register programming in the System Manager and Clock Manager and configuration of clocks in
multiple domains.
Note: When the EMAC interfaces to HPS I/O and register content is being transferred to a different clock
domain after a write operation, no further writes should occur to the same location until the first
write is updated. Otherwise, the second write operation does not get updated to the destination
clock domain. Thus, the delay between two writes to the same register location should be at least 4
cycles of the destination clock (PHY receive clock, PHY transmit clock, or PTP clock).
is accessed multiple times quickly, you must ensure that a minimum number of destination clock
cycles have occurred between accesses.
Note: If the EMAC signals are routed through the FPGA fabric and it is assumed that the transmit clock
supplied by the FPGA fabric switches within 6 transmit clock cycles, then the minimum time
required between two write accesses to the same register is 10 transmit clock cycles.
System Level EMAC Configuration Registers
In addition to the registers in the Ethernet Controller, there are other system level registers in the Clock
Manager, System Manager and Reset Manager that must be programmed in order to configure the EMAC
and its interfaces.
The following table gives a summary of the important System Manager clock register bits that control
operation of the EMAC. These register bits are static signals that must be set while the corresponding
EMAC is in reset.
Ethernet Media Access Controller
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Interrupts
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If the CSR
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