System Manager; Features Of The System Manager - Altera cyclone V Technical Reference

2016.10.28
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The system manager in the hard processor system (HPS) contains memory-mapped control and status
registers (CSRs) and logic to control system level functions as well as other modules in the HPS.
The system manager connects to the following modules in the HPS:
• Direct memory access (DMA) controller
• Ethernet media access controllers (EMAC0 and EMAC1)
• Microprocessor unit (MPU) subsystem
• NAND flash controller
• Secure Digital/MultiMediaCard (SD/MMC) controller
• Quad serial peripheral interface (SPI) flash controller
• USB 2.0 On-The-Go (OTG) controllers (USB0 and USB1)
• Watchdog timers

Features of the System Manager

Software accesses the CSRs in the system manager to control and monitor various functions in other HPS
modules that require external control signals. The system manager connects to these modules to perform
the following functions:
• Sends pause signals to pause the watchdog timers when the processors in the MPU subsystem are in
debug mode
• Selects the EMAC level 3 (L3) master signal options.
• Freezes the I/O pins after the HPS comes out of cold reset and during serial configuration.
• Selects the SD/MMC controller clock options and L3 master signal options.
• Selects the NAND flash controller bootstrap options and L3 master signal options.
• Selects USB controller L3 master signal options.
• Provides control over the DMA security settings when the HPS exits from reset.
• Provides boot source and clock source information that can be read during the boot process.
• Provides the capability to enable or disable an interface to the FPGA.
• Routes parity failure interrupts from the L1 caches to the Global Interrupt Controller.
• Sends error correction code (ECC) enable signals to all HPS modules with ECC-protected RAM.
• Provides the capability to inject errors during testing in the MPU L2 ECC-protected RAM.
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