Hps-Fpga Bridges Block Diagram And System Integration - Altera cyclone V Technical Reference

cv_5v4
2016.10.28

HPS-FPGA Bridges Block Diagram and System Integration

Figure 8-1: HPS-FPGA Bridge Connectivity
The following figure shows the HPS-FPGA bridges in the context of the FPGA fabric and the L3
interconnect to the HPS. Each master (M) and slave (S) interface is shown with its data width(s). The clock
domain for each interconnect is shown in parentheses.
The HPS-to-FPGA bridge is mastered by the level 3 (L3) main switch and the lightweight HPS-to-FPGA
bridge is mastered by the L3 slave peripheral switch.
The FPGA-to-HPS bridge masters the L3 main switch, allowing any master implemented in the FPGA
fabric to access most slaves in the HPS. For example, the FPGA-to-HPS bridge can access the accelerator
coherency port (ACP) of the Cortex-A9 MPU subsystem to perform cache-coherent accesses to the
SDRAM subsystem.
All three bridges contain global programmers view (GPV) registers. The GPV registers control the
behavior of the bridge. Access to the GPV registers of all three bridges is provided through the lightweight
HPS-to-FPGA bridge.
Related Information
• Clocks and Resets
Functional Description of the System Interconnect
•
Detailed information about connectivity, such as which masters have access to each bridge
HPS-FPGA Bridges
Send Feedback
32, 64, or 128 Bits
(h2f_axi_clk)
32 Bits
M
(l4_mp_clk)
S
AXI
AHB
(GPV)
HPS-to-FPGA
Bridge
S
AXI
64 Bits
(l3_main_clk)
M
AXI
(L3 Main Switch)
on page 8-51
HPS-FPGA Bridges Block Diagram and System Integration
FPGA Fabric
32 Bits
(h2f_lw_axi_clk)
32 Bits
(l4_mp_clk)
M M M
AHB AHB
AXI
Lightweight
HPS-to-FPGA Bridge
S
AXI (GPV)
32 Bits
(l4_mp_clk)
M
AXI
(L3 Slave Peripheral Switch)
L3 Interconnect
32, 64, or 128 Bits
(f2h_axi_clk)
S
S
AXI
AHB
(GPV)
FPGA-to-HPS
Bridge
M
AXI
64 Bits
(l3_main_clk)
S
AXI
(L3 Main Switch)
Altera Corporation
8-3